Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public

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Document Table of Contents

7.2.11. set_enable_a_constant_during_clk_disabled()

Prototype:

set_enable_a_constant_during_clk_disabled()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures that all signals are held constant if clken is deasserted.
Language support: Verilog HDL