Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

5.4.28. set_clken()

Prototype:

void set_clken(bit state)

Arguments:

Verilog HDL: bit state

VHDL: bit state, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the assertion and deassertion of the clock enable signal.
Language support: Verilog HDL, VHDL

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