Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

5.1. Timing

The following timing diagram illustrates the sequence of events for an Avalon-MM Master BFM. The Master BFM drives interleaved writes and reads when the readdatavalid signal is present. This diagram serves as a reference for the following discussion of API and events.
Figure 4. Avalon-MM Master Driving Interleaved Write and Read Transactions
Table 5.  Key to the AnnotationsThe following table lists the annotations used in the figure.
Symbol Description
Tinit The initial command latency, which is two cycles for transactions 1 and 2. This time is set by the API command set_command_init_latency.
Twt_1 The response wait time, which is three cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_response_wait_time command.
Twr waitrequest is always sampled #1 after the falling edge of clk.
Tidle The idle time after each transaction. This time is set by the command set_command_idle.
Trl_1 The response latency for the first read, which is 3 cycles. This is the time between the read command acceptance and the read response provided by the slave. The program gets this time using the get_response_latency command.

If an Avalon-MM slave component defines the readLatency interface property, the readdatavalid signal is not used. The readdatavalid signal is not necessary because the slave component has a fixed read latency.

For more information refer to the Avalon Interface Specifications.

Trl_2 The response latency for the second read, which is 3 cycles. The program gets this time using the get_response_latency command.
Twrl_1 The write response latency for the first write, which is 3 cycles. This is the time between when the write command acceptance and the write response is provided by the slave. The program gets this time using the get_response_latency command.
Sci_1–Sci_4 Signals when write or read commands are presented on the interface. The event name is signal_command_issued.
Src_1,Src_3 Signals write responses. The event name is signal_response_complete.
Src_2,Src_4 Signals read responses. The event name is signal_response_complete.
Satc Signals the end of the test. The event name is signal_all_transactions_complete
TID_1–TID_4 Reference number to identify each read or write transaction.
ID_1, ID_3 Reference number to identify each write transaction.
ID_2, ID_4 Reference number to identify each read transaction.
Figure 5. Avalon-MM Master Driving Write and Read Transactions with No readdatavalid SignalThe timing in the following figure shows the sequence of events for an Avalon-MM Master BFM. The Avalon-MM Master BFM drives a write followed by a read when the readdatavalid signal is not present.
Table 6.  Key to the Annotations The following table lists the annotations used in this figure.
Symbol Description
Tinit The initial command latency, which is 2 cycles for transactions 1 and 2. This time is set by the API command set_command_init_latency.
Twt_1 The response wait time, which is 3 cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_response_wait_time command.
Twt_2 The response wait time for the first read, which is 2 cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_response_wait_time command.
Twr waitrequest is always sampled #1 after the falling edge of clk.
Tidle The idle time after a transaction. This time is set by the command set_command_idle.
Sci_1–Sci_2 Signals when write and read commands are presented on the interface. The event name is signal_command_issued.
Src_1 Signals the first read response. The event name is signal_response_complete.
Satc Signals the end of the test. The event name is signal_all_transactions_complete.

Did you find the information on this page useful?

Characters remaining:

Feedback Message