Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Document Table of Contents

1.4. Application Example of BFMs

The figure below shows an Avalon-MM design with the following components:
  • An Avalon-MM device under test (DUT) that includes both Avalon-MM master and slave interfaces
  • An Avalon-ST DUT that includes both source and sink interfaces, although typical components might include a single Avalon interface.

This figure illustrates it is possible to write a testbench using a traditional VerilogHDL implementation or using SystemVerilog with VMM.

Figure 2. Avalon Verification IP Suite Testbench for Avalon-MM and Avalon-ST Interfaces

To verify a component with Avalon-MM interfaces, insert a monitor between the master BFM and the slave interface. To verify a component with Avalon-ST interfaces, insert a monitor between the source BFM and sink interface. You can insert a second monitor between the slave or sink BFM and the master or source interface of the DUT. You can inserted monitors anywhere in the system to provide protocol assertion checking and functional coverage reporting.

The test program drives the stimulus to the DUTs. The test program also determines whether the DUT behavior is correct, by analyzing the responses. The BFMs translate the test program stimuli. The BFMs create the signaling for the Avalon-MM and Avalon-ST protocols. The monitors verify Avalon protocol compliance and provide test coverage reports.