Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.14. set_enable_a_half_cycle_reset_legal()

Prototype:

set_enable_a_half_cycle_reset_legal()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures reset is asserted correctly.
Language support: Verilog HDL

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