Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents
Give Feedback

7.2.29.46. signal_read_response_complete

Prototype:

signal_read_response_complete

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Notifies the testbench that the read response has been received and inserted into the response queue.
Language support: Verilog HDL