Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

15.3.1. read()

Prototype:

read()

Arguments:

Verilog HDL: bit[CDT_ADDRESS_W-1:0] address

VHDL: data, bit[CDT_ADDRESS_W-1:0] address, bfm_id, req_if(bfm_id)

Returns:

logic[DATA_W-1:0]

Description:

Retrieves the memory content from an address you specify.
Language support: Verilog HDL, VHDL

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