Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

16.2.1.16. set_ci_clk_en()

Prototype:

void set_ci_clk_en()

Arguments:

Verilog HDL: bit enable

VHDL: bit enable, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the ci_clk_en signal synchronously with the clock.
Language support: Verilog HDL, VHDL

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