Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public

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Document Table of Contents

8.4.32. signal_src_ready

Prototype:

signal_src_ready

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Signals that the ready signal is asserted.
Language support: Verilog HDL