Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.29.44. signal_command_received

Prototype:

signal_command_received

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Notifies the testbench that a command was detected on the Avalon port. When this event is received, the testbench responds with a set_interface_wait_time call. This call dynamically backpressures the driving Avalon master.
Language support: Verilog HDL

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