Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

16.2.1.17. set_clock_enable_timeout()

Prototype:

void set_clock_enable_timeout()

Arguments:

Verilog HDL: int timeout

VHDL: int timeout, bfm_id, req_if

Returns:

void

Description:

Sets the timeout value for the clock enable. Sets the value to 0 (zero)to disable timeouts.
Language support: Verilog HDL, VHDL

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