Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

10.2.6. set_enable_a_valid_legal()

Prototype:

set_enable_a_valid_legal()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures valid is deasserted readyLatency cycles after ready is deasserted if the readyLatency is greater than 0.
Language support: Verilog HDL