Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

17.2.6. get_ci_clk_en()

Prototype:

void get_ci_clk_en(bit enable)

Arguments:

Verilog HDL: None

VHDL: clk_en, bfm_id, req_if(bfm_id)

Returns:

bit enable

Description:

Retrieves the clock enable signal.
Language support: Verilog HDL, VHDL