Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

8.4.25. set_transaction_sop()

Prototype:

set_transaction_sop(bit sop)

Arguments:

Verilog HDL: sop

VHDL: sop, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the status of the start of packet signal in the out-going transaction.
Language support: Verilog HDL, VHDL

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