Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

19.1.1. Running the Verilog HDL Testbench for a Single Avalon-MM Master and Slave Pair

  1. Unzip ug_avalon_verification.zip to a working directory.
  2. For the Quartus Prime Standard Edition software, open <working_dir>/avmm/avlmm1x1_verilog/avlm_avls_1x1.qsys.
  3. For the Quartus Prime Pro Edition software, specify the <working_dir>/avmm/avlmm1x1_verilog_pro/avlm_avls_1x1.qpf project file and <working_dir>/avmm/avlmm1x1_verilog_pro/avlm_avls_1x1.qsys system in the Open System dialog box.
  4. On the Generate menu, select Generate HDL.
  5. Specify the parameters shown in the following table:
    Table 28.  Generation Parameters
    Parameter Value
    Synthesis
    Create HDL design files for synthesis Verilog
    Create timing and resource estimates for third-party EDA synthesis tools Leave this option off
    Create block symbol file (.bsf) Leave this option on
    IP-XACT Leave this option off. (This parameter is only available in the Quartus Prime Pro Edition software.)
    Simulation
    Create simulation model Verilog
    Output Directory
    Path Accept the path specified. (This path is not shown for the Quartus Prime Pro Edition software.)
    Clear output directories for selected generation targets You can leave this parameter off the first time you generate.
  6. Close the Generate window.
  7. Start the ModelSim® simulator.
  8. To run the simulation, type the following command in your working directory:
    do run_simulation.tcl
    This command compiles all the required HDL files, elaborates, and runs the simulation.

Timing for a Write Burst with a Burst Count of Four

Figure 29. Timing for a Read with Burst Count of Three

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