Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.26. set_enable_a_write_burst_timeout()

Prototype:

set_enable_a_write_burst_timeout()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures that the write burst transfer is completed within maximum allowed timeout period. Disabled when write burst transfers are not supported or the write burst timeout period is less than 1 cycle.
Language support: Verilog HDL

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