Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

17.2.25. set_result_delay()

Prototype:

void set_result_delay()

Arguments:

Verilog HDL: ci_data_t delay

VHDL: ci_data_t delay, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the instruction result delay.
Language support: Verilog HDL, VHDL

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