Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

10.2.7.12. set_enable_c_error_in_middle_of_packet()

Prototype:

set_enable_c_error_in_middle_of_packet()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables a coverage point that ensures test coverage for the assertion of the error signal in the middle of a packet. It is disabled when the error signal is not supported.
Language support: Verilog HDL

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