Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Document Table of Contents
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18.2.1. Creating the Qsys Design

In this section you generate a testbench system in Qsys for the DUT.

Before you run the design file, unzip the ug_avalon_verification.zip file to a working directory on your hard drive. This location is referred to as <working_directory> .

  1. Launch the Quartus Prime software.
  2. On the File menu, click Open. Select st_bfm_project.qpf located in <working_directory>/ug_avalon_verification/avst/<quatus_version> .
  3. On the Tools menu, click Qsys or Qsys Pro.
  4. On the Qsys File menu, open st_bfm_qsys_tutorial.qsys. This is a blank Qsys system.
    For Quartus Prime Pro, you must also specify the st_bfm_project.qpf project file.
  5. Type fifo in the IP Catalog search box. From the search results, select the Avalon-ST Single Clock FIFO .
  6. In the parameter editor, change the parameter values to match the values listed in the following table.
    Table 25.  Avalon-ST Single Clock FIFO Parameter Values
    Parameters Value
    Symbols per beat 4
    Bits per symbol 8
    FIFO depth 2
    Channel width 3
    Error width 3
    Use packets On
    Use fill level Off
    Use store and forward Off
    Use almost full status Off
    Use almost empty status Off
    Enable explicit maxChannel Off
    Explicit maxChannel Off
  7. Click Finish.
  8. Right-click on the sc_fifo_0 component and select Rename. Rename the component to dut.
  9. On the System Contents tab, in the Export column, rename the exported interface names to match the names listed in the table.
    Table 26.  Avalon-ST Single Clock FIFO Exported Interface Names
    Interface Name Description Export Name
    clk Clock Input clk
    clk_reset Reset Input reset
    in Avalon Streaming Sink st_in
    out Avalon Streaming Source st_out
  10. Save st_bfm_qsys_tutorial.qsys.