Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.4. set_enable_a_beginbursttransfer_single_cycle()

Prototype:

set_enable_a_beginbursttransfer_single_cycle()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures beginbursttransfer is asserted for a single cycle regardless of the behavior of the waitrequest signal. It is disabled when beginbursttransfer is not used.
Language support: Verilog HDL

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