7. Avalon-MM Monitor
The Avalon-MM Monitor is implemented in SystemVerilog and uses the SystemVerilog Assertion (SVA) language. The SVA language is supported by the Synopsys VCS, and Mentor Graphics Questa simulators. If you are using ModelSim, the monitor component still compiles and simulates. However, the assertion checking is disabled.
The following figure shows a testbench that uses an Avalon-MM Monitor to test components with Avalon-MM interfaces. The monitor’s Avalon-MM Master interface is connected to a component’s Avalon-MM slave interface. An Avalon-MM Slave interface is connected to a component’s Avalon-MM master interface. The test program communicates with the monitor. The test program can use the monitor’s assertion checking and coverage groups to ensure that all legal parameter values for the DUT’s Avalon-MM interface are tested. The Avalon-MM Monitor also includes a transaction collector feature to collect and monitor transaction status.
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