Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.1. set_enable_a_address_align_with_data_width()

Prototype:

set_enable_a_address_align_with_data_width()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures the byte address that the master uses is aligned with the data width.
Language support: Verilog HDL

Did you find the information on this page useful?

Characters remaining:

Feedback Message