Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

10.2.4. set_enable_a_non_missing_endofpacket()

Prototype:

set_enable_a_non_missing_endofpacket()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures that the startofpacket signal is asserted between each two assertions of an endofpacket signal.
Language support: Verilog HDL

Did you find the information on this page useful?

Characters remaining:

Feedback Message