Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

8.4.18. set_response_timeout()

Prototype:

set_response_timeout(int cycles)

Arguments:

Verilog HDL: cycles

VHDL: cycles, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the number of cycles that have to elapse before a response timeout is asserted. Disable the time-out by setting the cycles argument to zero.
Language support: Verilog HDL, VHDL

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