Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.1. Parameters

The Avalon-MM Monitor supports the full range of signals defined for the Avalon-MM master and slave interfaces. You can customize the Avalon-MM master and slave interfaces using the parameters described in the following table.
Table 11.  Parameters for the Avalon-MM Monitor
Parameter Default Value Legal Values Description
Port Widths
Address width 32 N/A Address width in bits.
Symbol width 8 N/A Data symbol width in bits. The symbol width should be 8 for byte-oriented interfaces.
Number of symbols 4 N/A Numbers of symbols per word.
Burstcount width 3 N/A The width of the burst count in bits.
Readresponse width 8 N/A Read response signal width in bits.
Writeresponse width 8 N/A Write response signal width in bits.
Port Enables
Use the read signal On On/Off When On, the interface includes a read pin.
Use the write signal On On/Off When On, the interface includes a write pin.
Use the address signal On On/Off When On, the interface includes address pins.
Use the byte enable signal On On/Off When On, the interface includes byte_enable pins.
Use the burstcount signal On On/Off When On, the interface includes burstcount pins.
Use the readdata signal On On/Off When On, the interface includes a readdata pin.
Use the readdatavalid signal On On/Off When On, the interface includes a readdatavalid pin.
Use the writedata signal On On/Off When On, the interface includes a writedata pin.
Use the begintransfer signal Off On/Off When On, the interface includes writedata pins.
Use the beginbursttransfer signal Off On/Off When On, the interface includes a beginbursttransfer pins.
Use the waitrequest signal On On/Off When On, the interface includes a waitrequest pin.
Use the arbiterlock signal Off On/Off When On, the interface includes an arbiterlock pin.
Use the lock signal Off On/Off When On, the interface includes a lock pin.
Use the debugaccess signal Off On/Off When On, the interface includes a debugaccess pin.
Use the transactionid signal Off On/Off When On, the interface includes a transactionid pin.
Use the writeresponse signal Off On/Off When On, the interface includes a writeresponse pin.
Use the readresponse signal Off On/Off When On, the interface includes a readresponse pin.
Use the clken signals Off On/Off When On, the interface includes a clken pin.
Burst Attributes
Linewrap burst On On/Off When On, the address for bursts wraps instead of an incrementing. With a wrapping burst, when the address reaches a burst boundary, it wraps back to the previous burst boundary. Consequently, only the low order bits are used for addressing.
Burst on burst boundaries only On On/Off When On, memory bursts are aligned to the address size.
Miscellaneous
Read response timeout (cycles) 100 N/A Specifies when a timeout occurs if readdatavalid is not asserted.
Avalon write timeout (cycles) 100 N/A Specifies when a timeout occurs if a burst write transfer has not completed.
Waitrequest timeout (cycles) 1024 N/A Timeout period for the continuous assertion of waitrequest.
Maximum pending reads 1 N/A Specifies the maximum number of pipelined reads that can be pending.
Fixed read latency (cycles) 0 N/A Sets the read latency for fixed-latency slaves. Not used on interfaces that include the readdatavalid signal.
Maximum read latency (cycles) 100 N/A Specifies the maximum read latency in cycle for test coverage function
Maximum waitrequest read cycles (for coverage) 100 N/A Specifies the maximum wait time allowed for read cycle for coverage.
Maximum waitrequest write cycles (for coverage) 100 N/A Maximum wait time allowed for write cycle for coverage.
Maximum continuous read (cycles) 5 N/A Maximum continuous read time allowed for coverage.
Maximum continuous write (cycles) 5 N/A Maximum continuous write time allowed for coverage.
Maximum continuous waitrequest (cycles) 5 N/A Maximum continuous wait request time allowed for coverage.
Maximum continuous readdatavalid (cycles) 5 N/A Maximum continuous readdatavalid time allowed for coverage.
VHDL BFM ID 0 0–1023 For VHDL BFMs only. Use this option to assign a unique number to each BFM in the testbench design.
Timing
Fixed read wait time (cycles) 1 N/A For master interfaces that do not use the waitrequest signal. The read wait time indicates the number of cycles before the master responds to a read. The timing is as if the master asserted waitrequest for this number of cycles.
Fixed write wait time (cycles) 0 N/A For master interfaces that do not use the waitrequest signal. The write wait time indicates the number of cycles before the master accepts a write.
Registered waitrequest Off On/Off Specifies whether to turn on the register stage.
Registered Incoming Signals Off On/Off Specifies whether to register incoming signals.

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