Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

1.2. BFM Implementation

Most components in the Avalon Verification IP Suite BFMs are implemented in SystemVerilog. The exceptions are the Clock Source and Reset Source BFMs that are written in VHDL. The BFM components use primarily Verilog HDL with a few basic SystemVerilog constructs that are supported by ModelSim® - Intel FPGA Edition.

The Quartus II software version 13.0 and higher extends VHDL BFM support in Qsys. The VHDL BFMs wrap the SystemVerilog implementation and include additional logic to support VDHL.

Table 1.  BFM Language Support
BFM Verilog HDL Support VHDL Support
Clock Source and Reset Source Yes Yes
Avalon Interrupt Source and Sink Yes Version 13.0 and higher
Avalon-MM Master, Slave, and Monitor Yes Version 13.0 and higher
Avalon-ST Source, Sink, and Monitor Yes Version 13.0 and higher
Conduit and Tri-State Conduit Yes Version 14.0 and higher
External Memory Yes Version 13.0 and higher
Nios II Custom Instruction Master and Slave Yes Version 13.0 and higher

The VHDL BFM has four parts as shown in the figure below.

  • SystemVerilog BFM—Contains the BFM implementation and behavioral model, and the SystemVerilog API. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
  • VHDL package—Provides the VHDL API used to control the BFM and interface with your test program. The package contains VHDL procedures and events.
  • API handler logic—SystemVerilog logic block that translates your test program’s VHDL API calls to SystemVerilog API calls. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
  • API communication interface—Bridges the VHDL API to the API handler logic.
    Figure 1. VHDL Component BFM

The monitor components use the SystemVerilog Assertion (SVA) language and are supported only by simulators that support SVA, including:

  • ModelSim® - Intel FPGA Edition
  • Synopsys VCS
  • Mentor Graphics® Questa.

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