Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
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Document Table of Contents

1. Introduction to Avalon Verification IP Suite

Updated for:
Intel® Quartus® Prime Design Suite 20.4
The Avalon® Verification IP Suite provides bus functional models (BFMs) to simulate the behavior and facilitate the verification of IP. The Verification IP Suite includes BFMs for the following interfaces and components:
  • Avalon Memory-Mapped (Avalon-MM) master and slave interfaces
  • Avalon Streaming (Avalon-ST) source and sink interfaces
  • Conduit interfaces and Avalon Tri-State conduit (Avalon-TC) interfaces
  • Clock source and reset source
  • Interrupt source and sink
  • Custom instruction master and slave
  • External memory

This suite also provides the following monitors to verify the respective Avalon protocols:

  • Avalon-MM monitor
  • Avalon-ST monitor

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