Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

8.4.21. set_transaction_idles()

Prototype:

set_transaction_idles(bit[31:0] idle_cycles)

Arguments:

Verilog HDL: idle_cycles

VHDL: idle_cycles, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the number of idle cycles to elapse before driving the out-going transaction.
Language support: Verilog HDL, VHDL

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