Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

9.4.15. signal_fatal_error

Prototype:

signal_fatal_error

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Signals that a fatal error has occurred. It terminates the simulation.
Language support: Verilog HDL

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