Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

5.4.36. set_command_idle()

Prototype:

void set_command_idle(int idle, int index)

Arguments:

Verilog HDL: int idle, int index

VHDL: int idle, int index, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets idle cycles at the end of each transaction cycle. For read commands, idle cycles are inserted at the end of the command cycle. For burst write commands, idle cycles are inserted at the end of each write data cycle within the burst.
Language support: Verilog HDL, VHDL

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