Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.23. set_enable_a_register_incoming_signals()

Prototype:

set_enable_a_register_incoming_signals()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures waitrequest is asserted at all times and deasserts a single clock cycle after a read or write transaction.
Language support: Verilog HDL