Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.7. set_enable_a_begintransfer_single_cycle()

Prototype:

set_enable_a_begintransfer_single_cycle()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that ensures begintransfer is asserted for only 1 cycle and not reasserted for any single transfer, regardless of the status of the waitrequest signal.
Language support: Verilog HDL

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