Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

19.2.1. Running the Testbench for a Single Avalon-MM Master and Slave Pair

  1. Unzip ug_avalon_verification.zip to a working directory.
  2. For the Quartus Prime Standard Edition software, open <working_dir>/avlmm_1x1_vhdl/avlm_avls_1x1.qsys.
  3. For the Quartus Prime Pro Edition software, specify the <working_dir>/avlmm1x1_vhdl_pro/avlm_avls_1x1.qpf project and <working_dir>/avlmm1x1_vhdl_pro/avlm_avls_1x1.qsys system in the Open System dialog box.
  4. Complete the following steps to generate the testbench:
    1. On the Generate menu, select Generate HDL.
    2. Specify the parameters shown in the following table:
      Table 30.  Generation Parameters
      Parameter Value
      Synthesis
      Create HDL design files for synthesis VHDL
      Create timing and resource estimates for third-party EDA synthesis tools Leave this option off
      Create block symbol file (.bsf) Leave this option on
      Simulation
      Create simulation model VHDL
      Output Directory
      Path Accept the path specified. (This path is not shown for the Quartus Prime Pro Edition software.)
    3. Click Generate.
      The Qsys Generate window displays informational messages as it generates the testbench.
    4. Close the Generate window.
  5. To provide versioned libraries for the VHDL RTL simulation, run the following command:
    ./update.sh
    You must rerun ./update.sh each time you regenerate the testbench.
  6. Start the ModelSim® simulator.
  7. To run the simulation, type the following command in your working directory:
    do run_simulation.tcl
    This command compiles all the required HDL files, elaborates, and runs the simulation.
Figure 33. Timing for a Write Burst with a Burst Count of Five
Figure 34. Timing for a Read with a Burst Count of Six

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