Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

20. Document Revision History

The following table shows the revision history for this document.
Document Version Intel® Quartus® Prime Version Changes
2022.02.17 20.4 Updated the numbering of sections in Clock Source API.
2022.01.24 20.4 Changed the maximum legal value of the SRC_SYMBOLS_PER_BEAT and SRC_DATA_BITS_PER_SYMBOL parameters to 8192 in the Avalon Streaming Credit Source BFM and Avalon Streaming Credit Sink BFM sections.
2021.01.29 20.4

Replaced the get_response_write_response() API with get_write_response_status() in the Avalon-MM Master BFM chapter.

Updated the API set_write_response_status() in the Avalon-MM Slave BFM chapter.

2020.12.14 20.4

Added three new APIs to the Avalon® Streaming Credit Source BFM chapter: get_outstanding_credit(), set_transaction_channel() and set_transaction_error().

Also added three new APIs to the Avalon® Streaming Credit Sink BFM chapter: get_outstanding_credit(), get_transaction_channel() and get_transaction_error().

2020.04.24 20.1 Added the chapters Avalon® Streaming Credit Source BFM and Avalon® Streaming Credit Sink BFM.
2019.04.03 16.1 Removed VHDL from the Language Support field for the APIs clock_stop(), get_run_state() and get_version().
2016.12.13 16.1

Made the following changes:

  • Restored missing Avalon-ST files to ug_avalon_verification.zip.
  • Added support for Quartus® Prime Pro Edition software.
  • Simplified design creation for both the Avalon-ST and Avalon-MM designs.
  • Corrected minor errors and typos.
2015.06.04 15.1 Made the following changes:
  • Updated the definition of set_response_latency for the Avalon-MM slave BFM.
  • Corrected language support for the Clock Source BFM and Reset Source BFM. These BFMs support both Verilog HDL and VHDL.
  • Updated the name of the .zip file of example designs to ug_avalon_verification.zip.
June 2014 3.3 Made the following changes:
  • Revised the VHDL API arguments. The following changes were made for all VHDL procedures:
    • Removed the req_if argument from event_* procedures.
    • Changed the req_if argument to req_if(bfm_id) for all set_*, get_*, push_*, and pop_* procedures.
    • Changed the first argument to the get_* procedures to the return value.
  • Added support for VHDL for the conduit and tri-state conduit interfaces.
  • Updated Qsys tutorial to work in with Quartus II 14.0 software.
  • Added Avalon-MM Testbenches for Verilog HDL and VHDL . This chapter provides the following testbenches:
    • Verilog HDL testbench for single Avalon-MM Master and Slave pair.
    • Verilog HDL testbench for 2 Avalon-MM Masters that both connect to 2 Avalon-MM Slaves.
    • VHDL testbench for single Avalon-MM Master and Slave pair.
    • Verilog HDL testbench for 2 Avalon-MM Masters that both connect to 2 Avalon-MM Slaves.
  • Reformatted.
May 2013 3.2 Added information on VHDL support for verification IP.

Removed information on the following wrappers. These wrappers are not supported in the Quartus II software version 13.0 and higher.

  • Avalon-MM master BFM with Avalon-ST API wrapper
  • Avalon-MM slave BFM with Avalon-ST API wrapper
  • Avalon-ST source BFM with Avalon-ST API wrapper
  • Avalon-ST sink BFM with Avalon-ST API wrapper

    Removed references to SOPC Builder.

June 2012 3.1
  • Updated SOPC Tutorial chapter.
  • Updated Qsys Tutorial chapter.