The Avalon® Verification IP Suite provides bus functional models (BFMs) to simulate the behavior of various Avalon interfaces. It also provides monitors to verify Avalon protocols. This suite facilitates the verification of intellectual property (IP) that includes Avalon interfaces.
Figure 1 shows the block diagram of a verification testbench using the Avalon Verification IP Suite. You create the test system by connecting the suite components to the design under test. In the test module, you control the test flow by communicating to the Avalon Verification IP Suite components via the application programming interface (API).
Figure 1. Verification Testbench Using Avalon Verification IP Suite