Avalon® Verification IP Suite Design Example

The Avalon® Verification IP Suite provides bus functional models (BFMs) to simulate the behavior of various Avalon interfaces. It also provides monitors to verify Avalon protocols. This suite facilitates the verification of intellectual property (IP) that includes Avalon interfaces.

Figure 1 shows the block diagram of a verification testbench using the Avalon Verification IP Suite. You create the test system by connecting the suite components to the design under test. In the test module, you control the test flow by communicating to the Avalon Verification IP Suite components via the application programming interface (API).

Figure 1. Verification Testbench Using Avalon Verification IP Suite

This design example demonstrates how you can use Avalon Verification IP Suite to verify a design under test. As this is a simulation-based design, using this design doesn't require any Intel® FPGA development kits. However, you need to have the ModelSim* simulation tool installed on your machine.

Using This Design Example

To run this example, download the ug_avalon_verification.zip and unzip it to your hard drive. Then, follow the instructions in Avalon Verification IP Suite User Guide (PDF).

Related Links

For more information on Avalon interface specifications, go to:

Design Examples Disclaimer

The use of this design example is subject to the terms of the Intel® Design Example License Agreement.

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.