ID 683841
Date 7/24/2019
Public

## 8.3. Signal Descriptions

The following tables lists the signals of the controller’s Avalon-MM slave interface.

Table 102.  Avalon-MM Slave Read Signals

UniPHY Signal Name

Arria 10 Signal Name

Width (UniPHY)

Width (Arria 10)

Direction

Avalon-MM Signal Type

avl_r_ready

amm_ready_0

1

1

Out

waitrequest_n

avl_r_read_req

amm_read_0

1

1

In

read

avl_r_addr

amm_address_0

15–25

17–23

In

address

avl_r_rdata_valid

amm_readdatavalid_0

1

1

Out

readdatavalid

avl_r_rdata

amm_readdata_0

9, 18, 36 (or 8, 16, 32 if power-of-2-bus is enabled in the controller)

9, 18, 36 (or 8, 16, 32 if power-of-2-bus is enabled in the controller)

Out

readdata

avl_r_size

amm_burstcount_0

log_2(MAX_BURST_SIZE) + 1

ceil(log2(CTRL_QDR2_AVL_MAX_BURST_COUNT+1))

In

burstcount

Note: To obtain the actual signal width, you must multiply the widths in the above table by the data width ratio and the width expansion ratio.
Table 103.  Avalon-MM Slave Write Signals

UniPHY Signal Name

Arria 10 Signal Name

Width (UniPHY)

Width (Arria 10)

Direction

Avalon-MM Signal Type

avl_w_ready

amm_ready_1

1

1

Out

waitrequest_n

avl_w_write_req

amm_write_1

1

1

In

write

avl_w_addr

amm_address_1

15–25

17–23

In

address

avl_w_wdata

amm_writedata_1

9, 18, 36 (or 8, 16, 32 if power-of-2-bus is enabled in the controller)

9, 18, 36 (or 8, 16, 32 if power-of-2-bus is enabled in the controller)

In

writedata

avl_w_be

amm_byteenable_1

1,2,4

1,2,4

In

byteenable

avl_w_size

amm_burstcount_1

log_2(MAX_BURST_SIZE) + 1

ceil(log2(CTRL_QDR2_AVL_MAX_BURST_COUNT+1))

In

burstcount

Note: To obtain the actual signal width, you must multiply the widths in the above table by the data width ratio and the width expansion ratio.