External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

11.4. RLDRAM 3 Controller with Arria 10 EMIF Interfaces

The following table lists the RLDRAM 3 signals available for each interface when using Arria 10 EMIF IP.

Signal

Interface Type

Description

pll_ref_clk interface
pll_ref_clock Clock input Clock input to the PLL inside EMIF.
afi_clk_interface
afi_clock Clock output AFI clock output from the PLL inside EMIF.
afi_half_clk_interface
afi_half_clock Clock output AFI clock output from the PLL inside EMIF running at half speed.
Memory interface
mem_a Conduit Interface signal between the PHY and the memory device.
mem_ba
mem_ck
mem_ck_n
mem_cs_n
mem_dk
mem_dk_n
mem_dm
mem_dq
mem_qk
mem_qk_n
mem_ref_n
mem_we_n
mem_reset_n
Status interface
local_init_done Conduit Memory interface status signal.
local_cal_success
local_cal_fail
local_cal_request
oct interface
oct_rzqin Conduit OCT reference resistor pins for RZQ.
afi_interface
afi_addr Avalon-MM slave Altera PHY interface (AFI) signal between the PHY and the memory controller.
afi_ba
afi_cs_n
afi_we_n
afi_ref_n
afi_wdata_valid
afi_wdata
afi_dm
afi_rdata
afi_rdata_en_full
afi_rdata_valid
afi_rst_n
afi_cal_success
afi_cal_fail
afi_wlat
afi_rlat

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