External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.16.1. Restrictions on I/O Bank Usage for Arria® 10 EMIF IP with HPS

Only certain Arria® 10 I/O banks can be used to implement Arria® 10 EMIF IP with the Arria® 10 Hard Processor Subsystem. If both Arria® 10 HPS EMIF IP and non-HPS Arria® 10 EMIF IP are implemented, you must place the non-HPS EMIF IP in a different I/O column than the HPS EMIF IP.

The restrictions on I/O bank usage result from the Arria® 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed.

The following diagram illustrates the use of I/O banks and lanes for various EMIF-HPS data widths:

Figure 109. I/O Banks and Lanes Usage

You should refer to the pinout file for your device and package for detailed information. Banks and pins used for HPS access to a DDR interface are labeled HPS_DDR in the HPS Function column of the pinout file.

By default, the Arria® 10 External Memory Interface for HPS IP core together with the Quartus Prime Fitter automatically implement the correct pin-out for HPS EMIF without you having to implement additional constraints. If, for any reason, you must modify the default pin-out, you must adhere to the following requirements, which are specific to HPS EMIF:

  1. Within a single data lane (which implements a single x8 DQS group):
    1. DQ pins must use pins at indices 1, 2, 3, 6, 7, 8, 9, 10. You may swap the locations between the DQ bits (that is, you may swap location of DQ[0] and DQ[3]) so long as the resulting pin-out uses pins at these indices only.
    2. DM/DBI pin must use pin at index 11. There is no flexibility.
    3. DQS/DQS# must use pins at index 4 and 5. There is no flexibility.
  2. Assignment of data lanes must be as illustrated in the above figure. You are allowed to swap the locations of entire byte lanes (that is, you may swap locations of byte 0 and byte 3) so long as the resulting pin-out uses only the lanes permitted by your HPS EMIF configuration, as shown in the above figure.
  3. You must not change placement of the address and command pins from the default.
  4. You may place the alert# pin at any available pin location in either a data lane or an address and command lane.

To override the default generated pin assignments, comment out the relevant HPS_LOCATION assignments in the .qip file, and add your own location assignments (using set_location_assignment) in the .qsf file.

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