The calibration process uses the external RZQ reference resistor to determine the optimal settings for the I/O buffer, to meet the specified calibrated I/O standards on the FPGA. OCT Calibration only affects the I/O pin that is connected to the RZQ resistor; therefore, memory traffic is not interrupted during the calibration phase.
Upon completion of the calibration process, the updated calibration settings are applied to the I/O buffers. The memory traffic is halted momentarily by placing the memory into self-refresh mode; this ensures that the data bus is idle and no glitches are created by the I/O buffers during the buffer update. The buffer is updated as soon as the memory enters self-refresh mode. The memory interface exits self-refresh mode when the buffer update is complete and new read or write requests are detected on the Avalon bus. The controller remains in self-refresh mode until a new command is detected. OCT calibration continues to occur even if the memory is still in self refresh mode. Upon detection of a new command, the controller issues a self-refresh exit command to the memory, followed by a memory-side ZQ calibration short duration (ZQCS) command. Memory traffic resumes when the memory DLL has re-locked.
If you disable the periodic OCT recalibration engine, the calibration process occurs only once during device configuration. In this operating mode, the calibrated OCT settings can vary across temperature as specified by the calibration accuracy ranges listed in the Arria 10 Device Handbook. The DDR external timing report automatically factors in the effect of enabling or disabling the periodic OCT recalibration engine when calculating the total amount of external I/O transfer margin.
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