External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents NIOS II-based Sequencer Tracking Manager

The Tracking Manager detects the effects of voltage and temperature variations that can occur on the memory device over time resulting in reduced margins, and adjusts the DQS enable delay as necessary to maintain adequate operating margins.

The Tracking Manager briefly assumes control of the AFI interface after each memory refresh cycle, issuing a read routine to the RW Manager, and then sampling the DQS tracking. Ideally, the falling edge of the DQS enable signal would align to the last rising edge of the raw DQS signal from the memory device. The Tracking Manager determines whether the DQS enable signal is leading or trailing the raw DQS signal.

Each time a refresh occurs, the Tracking Manager takes a sample of the raw DQS signal; any adjustments of the DQS enable signal occur only after sufficient samples of raw DQS have been taken. When the Tracking Manager determines that the DQS enable signal is either leading or lagging the raw DQS signal, it adjusts the DQS enable appropriately.

The following figure shows the Tracking manager signals.

Figure 7. Tracking Manager Signals

Some notes on Tracking Manager operation:

  • The time taken by the Tracking Manager is arbitrary; if the period taken exceeds the refresh period, the Tracking Manager handles memory refresh.
  • afi_seq_busy should go high fewer than 10 clock cycles after afi_ctl_refresh_done or afi_ctl_long_idle is asserted.
  • afi_refresh_done should deassert fewer than 10 clock cycles after afi_seq_busy deasserts.
  • afi_ctl_long_idle causes the Tracking Manager to execute an algorithm different than periodic refresh; use afi_ctl_long_idle when a long session has elapsed without a periodic refresh.
  • The Tracking Manager is instantiated into the sequencer system when DQS Tracking is turned on.
    Table 1.  Configurations Supporting DQS Tracking

    Device Family


    Memory Clock Frequency

    Arria V (GX/GT/SX/ST) , Cyclone V

    LPDDR2 (single rank)

    All frequencies.

    Arria V (GX/GT/SX/ST)

    DDR3 (single rank)

    450 MHz or higher for speed grade 5, or higher than 534 MHz.

    Arria V GZ, Stratix V (E/GS/GT/GX)

    750 MHz or higher.

  • If you do not want to use DQS tracking, you can disable it (at your own risk), by opening the Verilog file <variant_name>_if0_c0.v in an editor, and changing the value of the USE_DQS_TRACKING parameter from 1 to 0.