External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.6.1.1. Logical Connections

The following logical connections exist in an Arria® 10 EMIF IP core.
Table 43.  Logical Connections Table
Logical Connection Description
afi_conduit_end

(Conduit)

The Altera PHY Interface (AFI) connects a memory controller to the PHY. This interface is exposed only when you configure the memory interface in PHY-Only mode. The interface is synchronous to the afi_clk clock and afi_reset_n reset.

afi_clk_conduit_end

(Conduit)

Use this clock signal to clock the soft controller logic. The afi_clk is an output clock coming from the PHY when the memory interface is in PHY-Only mode. The phase of afi_clk is adjusted dynamically by hard circuitry for the best data transfer between FPGA core logic and periphery logic with maximum timing margin. Multiple memory interface instances can share a single afi_clk using the Core Clocks Sharing option during IP generation.

afi_half_clk_conduit_end

(Conduit)

This clock runs at half the frequency of afi_lk. It is exposed only when the memory interface is in PHY-Only mode.

afi_reset_n_conduit_end

(Conduit)

This single-bit reset provides a synchronized reset output. Use this signal to reset all registers that are clocked by either afi_clk or afi_half_clk.

cal_debug_avalon_slave

(Avalon Slave/Target)

This interface is exposed when the EMIF Debug Toolkit/On-chip Debug Port option is set to Export. This interface can be connected to an Arria® 10 External Memory Interface Debug Component to allow EMIF Debug Toolkit access, or it can be used directly by user logic to access calibration diagnostic data.

cal_debug_clk_clock_sink

(Clock Input)

This clock is used for the cal_debug_avalon_slave interface. It can be connected to the emif_usr_clk_clock_source interface.

cal_debug_reset_reset_sink

(Reset Input)

This reset is used for the cal_debug_avalon_slave interface. It can be connected to the emif_usr_reset_reset_source interface.

cal_debug_out_avalon_master

(Avalon Master/Source)

This interface is exposed when the Enable Daisy-Chaining for EMIF Debug Toolkit/On-Chip Debug Port option is enabled. Connect this interface to the cal_debug_avalon_slave interface of the next EMIF instance in the same I/O column.

cal_debug_out_clk_clock_source

(Clock Output)

This interface should be connected to the cal_debug_clk_clock_sink interface of the next EMIF instance in the same I/O column (similar to cal_debug_out_avalon_master).

cal_debug_out_reset_reset_source

(Reset Output)

This interface should be connected to the cal_debug_reset_reset_sink interface of the next EMIF instance in the same I/O column (similar to cal_debug_out_avalon_master).

effmon_csr_avalon_slave

(Avalon Slave/Target)

This interface allows access to the Efficiency Monitor CSR. For more information, see the documentation on the UniPHY Efficiency Monitor.

global_reset_reset_sink

(Reset Input)

This single-wire input port is the asynchronous reset input for the EMIF core.

pll_ref_clk_clock_sink

(Clock Input)

This single-wire input port connects the external PLL reference clock to the EMIF core. Multiple EMIF cores may share a PLL reference clock source, provided the restrictions outlined in the PLL and PLL Reference Clock Network section are observed.

oct_conduit_end

(Conduit)

This logical port is connected to an OCT pin and provides calibrated reference data for EMIF cores with pins that use signaling standards that require on-chip termination. Depending on the I/O standard, reference voltage, and memory protocol, multiple EMIF cores may share a single OCT pin.

mem_conduit_end

(Conduit)

This logical conduit can attach an Altera Memory Model to an EMIF core for simulation. Memory models for various protocols are available under the Memories and Memory ControllersExternal Memory InterfacesMemory Models section of the component library in Qsys. You must ensure that all configuration parameters for the memory model match the configuration parameters of the EMIF core.

status_conduit_end

(Conduit)

The status conduit exports two signals that can be sampled to determine if the calibration operation passed or failed for that core.

emif_usr_reset_reset_source

(Reset Output)

This single-bit reset output provides a synchronized reset output that should be used to reset all components that are synchronously connected to the EMIF core. Assertion of the global reset input triggers an assertion of this output as well, therefore you should rely on this signal only as a reset source for all components connected to the EMIF core.

emif_usr_clk_clock_source

(Clock Output)

Use this single-bit clock output to clock all logic connected to the EMIF core. The phase of this clock signal is adjusted dynamically by circuitry in the EMIF core such that data can be transferred between core logic and periphery registers with maximum timing margin. Drive all logic connected to the EMIF core with this clock signal. Other clock sources generated from the same reference clock or even the same PLL may have unknown phase relationships. Multiple EMIF cores can share a single core clock using the Core Clocks Sharing option described in the Example Design tab of the parameter editor.

ctrl_amm_avalon_slave

(Avalon Slave/Target)

This Avalon target port initiates read or write commands to the controller. Refer to the Avalon Interface Specification for more information on how to design cores that comply to the Avalon Bus Specification.

For DDR3, DDR4, and LPDDR3 protocols with the hard PHY and hard controller configuration and an AVL slave interface exposed, ctrl_amm_avalon_slave is renamed to crtl_amm_avalon_slave_0.

For QDR II, QDR II+, and QDR II+ Xtreme interfaces with hard PHY and soft controller, separate read and write connections are used. ctrl_amm_avalon_slave_0 is the read port and ctrl_amm_avalon_slave_1 is the write port.

For QDR-IV interfaces with hard PHY and soft controller operating at quarter rate, a total of eight separate Avalon interfaces (named ctrl_amm_avalon_slave_0 to ctrl_amm_avalon_slave_7) are used to maximize bus efficiency.

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