3.6.2. File Sets
This directory contains only the files required to integrate a generated EMIF core into a larger design. This directory contains:
Note: The top-level HDL file is generated in the root folder as <core_name>.v (or <core_name .vhd> for VHDL designs). You can reopen this file in the parameter editor if you want to modify the EMIF core parameters and regenerate the design.
This directory contains the simulation fileset for the generated EMIF core. These files can be integrated into a larger simulation project. For convenience, simulation scripts for compiling the core are provided in the /mentor, /cadence, /synopsys, and /riviera subdirectories.
The top-level HDL file, <core_name>.v (or <core_name>.vhd) is located in this folder, and all remaining HDL files are placed in the /altera_emif_arch_nf subfolder, with the customized data sheet. The contents of this directory are not intended for synthesis.
This directory contains a set of TCL scripts, QSYS project files and README files for the complete synthesis and simulation example designs. You can invoke these scripts to generate a standalone fully-synthesizable project complete with an example driver, or a standalone simulation design complete with an example driver and a memory model.
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