External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

16.7.4. Eye Diagram

The Generate Eye Diagram feature allows you to create read and write eye diagrams for each pin in your memory interface, for Arria 10 and later families.

The Generate Eye Diagram feature uses calibration data patterns to determine margins at each Vref setting on both the FPGA pins and the memory device pins. A full calibration is done for each Vref setting. Other settings, such as DQ delay chains, will change for each calibration. At the end of a Generate Eye Diagram command, a default calibration is run to restore original behavior

The Generate Eye Diagram feature is available for DDR4 and QDR-IV protocols, on Arria 10 devices.

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