External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.16. Arria® 10 EMIF for Hard Processor Subsystem

The Arria® 10 EMIF IP can enable the Arria® 10 Hard Processor Subsystem (HPS) to access external DRAM memory devices.

To enable connectivity between the Arria® 10 HPS and the Arria® 10 EMIF IP, you must create and configure an instance of the Arria® 10 External Memory Interface for HPS IP core, and use Qsys to connect it to the Arria® 10 Hard Processor Subsystem instance in your system.

Supported Modes

The Arria® 10 Hard Processor Subsystem is compatible with the following external memory configurations:

Protocol DDR3, DDR4
Maximum memory clock frequency

DDR3: 1.067 GHz

DDR4: 1.333 GHz

Configuration Hard PHY with hard memory controller
Clock rate of PHY and hard memory controller Half-rate
Data width (without ECC) 16-bit, 32-bit, 64-bit 2
Data width (with ECC) 24-bit, 40-bit, 72-bit 2
DQ width per group x8
Maximum number of I/O lanes for address/command 3
Memory format Discrete, UDIMM, SODIMM, RDIMM
Ranks / CS# width Up to 2
Notes to table:
  1. Only Arria® 10 devices with a special ordering code support 64-bit and 72-bit data widths; all other devices support only to 32-bit data widths.
Note: Arria 10 HPS EMIF IP does not currently support SmartVID.

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