2.4.8. Stratix® 10 EMIF Architecture: PLL Reference Clock Networks
Stratix® 10 external memory interfaces that span multiple banks use the PLL in each bank. (Some previous device families relied on a single PLL with clock signals broadcast to all I/Os by a clock network.) The Stratix® 10 architecture allows for relatively short PHY clock networks, reducing jitter and duty-cycle distortion.
The following mechanisms ensure that the clock outputs of individual PLLs in a multi-bank interface remain in phase:
- A single PLL reference clock source feeds all PLLs. The reference clock signal reaches the PLLs by a balanced PLL reference clock tree. The Quartus Prime software automatically configures the PLL reference clock tree so that it spans the correct number of banks.
- The EMIF IP sets the PLL M and N values appropriately to maintain synchronization among the clock dividers across the PLLs. This requirement restricts the legal PLL reference clock frequencies for a given memory interface frequency and clock rate. The Stratix 10 EMIF IP parameter editor automatically calculates and displays the set of legal PLL reference clock frequencies. If you plan to use an on-board oscillator, you must ensure that its frequency matches the PLL reference clock frequency that you select from the displayed list. The correct M and N values of the PLLs are set automatically based on the PLL reference clock frequency that you select.
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