External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.6.5. ECC in Arria® 10 EMIF IP

The ECC (error correction code) is a soft component of the Arria® 10 EMIF IP that reduces the chance of errors when reading and writing to external memory. ECC allows correction of single-bit errors and reduces the chances of system failure.

The ECC component includes an encoder, decoder, write FIFO buffer, and modification logic, to allow read-modify-write operations. The ECC code employs standard Hamming logic to correct single-bit errors and to detect double-bit errors. ECC is available in 16, 24, 40, and 72 bit widths.

When writing data to memory, the encoder creates ECC bits and writes them together with the regular data. When reading from memory, the decoder checks the ECC bits and regular data, and passes the regular data unchanged if no errors are detected. If a single-bit error is detected, the ECC logic corrects the error and passes the regular data. If more than a single-bit error is detected, the ECC logic sets a flag to indicate the error.

Read-modify-write operations can occur in the following circumstances:
  • A partial write in data mask mode with ECC enabled, where at least one memory burst of byte-enable is not all ones or all zeros.
  • Auto-correction with ECC enabled. This is usually a dummy write issued by the auto-correction logic to correct the memory content when a single-bit error is detected. The read-modify-write reads back the data, corrects the single-bit error, and writes the data back.

The additional overhead associated with read-modify-write operations can severely reduce memory interface efficiency. For best efficiency, you should design traffic patterns to avoid read-modify-write operations wherever possible, such as by minimizing the number of partial writes in ECC mode.

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