External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Document Table of Contents ECC Components

The ECC logic communicates with user logic via an Avalon-MM interface, and with the hard memory controller via an Avalon-ST interface

ECC Encoder

The ECC encoder consists of a x64/x72 encoder IP core capable of single-bit error correction and double-bit error detection. The encoder takes 64 bits input and converts it to 72 bits output, where the 8 additional bits are ECC code. The encoder supports any input data width less than 64-bits. Any unused input data bits are set to zero.

ECC Decoder

The ECC decoder consists of a x72/x64 decoder IP core capable of double-bit error detection. The decoder takes 72 bits input and converts it to 64 bits output. The decoder also produces single-bit error and double-bit error information. The decoder controls the user read data valid signal; when read data is intended for partial write, the user read data valid signal is deasserted, because the read data is meant for merging, not for the user.

Partial Write Data FIFO Buffer

The Partial Write Data FIFO Buffer is implemented in soft logic to store partial write data and byte enable. Data and byte enable are popped and merged with the returned read data. A partial write can occur in the following situations:
  • At least one memory burst of byte enable is not all ones or all zeroes.
  • Non data masked mode, where all memory bursts of byte enable are not all ones.
  • A dummy write with auto-correction logic, where all memory bursts of byte enable are all zeroes. (You might use a dummy write when correcting memory content with a single-bit error.)

Merging Logic

Merge return partial read data with write data based on byte enabled popped from the FIFO buffer, and send it to the ECC encoder.

Pointer FIFO Buffer

The pointer FIFO buffer is implemented in soft logic to store write data pointers. The ECC logic refers to the pointers when sending write data to the data buffer control (DBC). The pointers serve to overwrite existing write data in the data buffer during a read-modify-write process.

Partial Logic

Partial logic decodes byte enable information and distinguishes between normal and partial writes.

Memory Mode Register Interface

The Memory Mode Register (MMR) interface is an Avalon-based interface through which core logic can access debug signals and sideband operation requests in the hard memory controller.

The MMR logic routes ECC-related operations to an MMR register implemented in soft logic, and returns the ECC information via an Avalon-MM interface. The MMR logic tracks single-bit and double-bit error status, and provides the following information:
  • Interrupt status.
  • Single-bit error and double-bit error status.
  • Single-bit error and double-bit error counts, to a maximum of 15. (If more than 15 errors occur, the count will overflow.)
  • Address of the last error.

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