External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

9.1.1. Avalon-MM Slave Read and Write Interfaces

To maximize available bandwidth utilization, the QDR-IV external memory controller provides eight separate bidirectional Avalon interfaces—one channel for each of the two QDR-IV data ports in each of the four memory time slots. At the memory device, the PHY ensures that port A commands are issued on the rising edge of the clock, and port B commands are issued on the falling edge of the clock.

The Avalon finite state machine (FSM) implements the standard Avalon-MM interface for each channel. New commands arrive in a queue, before being sent to the PHY by the scheduler. The scheduler ensures that bank policy and bus turnaround restrictions are met. The controller handles address/data bus inversion, if you have enabled those features.

The controller schedules commands in a simple round-robin fashion, always maintaining the time slot relationship shown in the following table. At each AFI cycle, the scheduler attempts to issue up to eight commands—one from each channel. If a particular command cannot be issued due to bank policy or bus turnaround violations, only commands from the preceding channels are issued. The remaining commands are issued in the following one or more cycles, depending on whether further violations occur. Read data passes through without the controller registering it, after AFI to Avalon bus conversion. The PHY implements read latency requirements.

Table 104.  Avalon-MM to Memory Time Slot and Port Mapping
Avalon-MM Slave Interface Memory Time Slot Memory Port
0 0 A
1 0 B
2 1 A
3 1 B
4 2 A
5 2 B
6 3 A
7 3 B