External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.13.3.3. AFI Write Data Signals

Write Data Signals for AFI 3.0 control the data, data mask, and strobe signals passed to the memory device during write operations.
Table 11.  Write Data Signals

Signal Name

Direction

Width

Description

afi_dqs_burst

Input

AFI_WRITE_DQS_WIDTH

Controls the enable on the strobe (DQS) pins for DDR2, DDR3, and LPDDR2 memory devices. When this signal is asserted, mem_dqs and mem_dqsn are driven.

This signal must be asserted before afi_ wdata_valid to implement the write preamble, and must be driven for the correct duration to generate a correctly timed mem_dqs signal.

afi_wdata_valid

Input

AFI_WRITE_DQS_WIDTH

Write data valid signal. This signal controls the output enable on the data and data mask pins.

afi_wdata

Input

AFI_DQ_WIDTH

Write data signal to send to the memory device at double-data rate. This signal controls the PHY’s mem_dq output.

afi_dm

Input

AFI_DM_WIDTH

Data mask. This signal controls the PHY’s mem_dm signal for DDR2, DDR3, LPDDR2 and RLDRAM II memory devices.)

afi_bws_n

Input

AFI_DM_WIDTH

Data mask. This signal controls the PHY’s mem_bws_n signal for QDR II/II+ memory devices.

afi_wrank

Input

AFI_WRANK_WIDTH

Shadow register signal. Signal indicating the rank to which the controller is writing, so that the PHY can switch to the appropriate setting. Signal timing is identical to afi_dqs_burst; that is, afi_ wrank must be asserted at the same time as afi_dqs_burst, and must be of the same duration.

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