External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.13.3.4. AFI Read Data Signals

Read Data Signals for AFI 3.0 control the data sent from the memory device during read operations.

Table 12.  Read Data Signals

Signal Name

Direction

Width

Description

afi_rdata_en

Input

AFI_RATE_RATIO

Read data enable. Indicates that the memory controller is currently performing a read operation. This signal is held high only for cycles of relevant data (read data masking).If this signal is aligned to even clock cycles, it is possible to use 1-bit even in half-rate mode (i.e., AFI_RATE=2).

afi_rdata_en_full

Input

AFI_RATE_RATIO

Read data enable full. Indicates that the memory controller is currently performing a read operation. This signal is held high for the entire read burst.If this signal is aligned to even clock cycles, it is possible to use 1-bit even in half-rate mode (i.e., AFI_RATE=2).

afi_rdata

Output

AFI_DQ_WIDTH

Read data from the memory device. This data is considered valid only when afi_rdata_valid is asserted by the PHY.

afi_rdata_valid

Output

AFI_RATE_RATIO

Read data valid. When asserted, this signal indicates that the afi_rdata bus is valid. If this signal is aligned to even clock cycles, it is possible to use 1-bit even in half-rate mode (i.e., AFI_RATE=2).

afi_rrank

Input

AFI_RRANK_WIDTH

Shadow register signal. Signal indicating the rank from which the controller is reading, so that the PHY can switch to the appropriate setting. Must be asserted at the same time as afi_rdata_en when issuing a read command, and once asserted, must remain unchanged until the controller issues a new read command to another rank.

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